The present invention relates in general to circuits for generating clocks using a voltage-controlled oscillator circuit.
Phase-locked loops (PLL""s) have been widely used in high-speed communication systems because PLL""s efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select high performance with nominal power supply voltages and high frequency clock operation or low performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits must support very aggressive power/energy management techniques. For the PLL this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing and alternate low frequency clocking. Dynamic implies that the PLL is able to support changes in the output frequency and logic supply voltage without requiring the system to stop operation or waiting for the PLL clock to reacquire lock.
Using a PLL or delay-locked loop (DLL) has advantages in a battery powered system because a PLL is able to receive a lower frequency reference frequency from a stable oscillator to generate system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency. The prior art has described ways of selecting operating points of voltage and frequency statically, for example stopping execution while allow the PLL to frequency lock to a new frequency. This slows system operations and complicates system design.
One of the key circuits in a PLL is a voltage-controlled oscillator (VCO). Circuits in the PLL generate an error voltage that is coupled to the VCO to control the frequency of the VCO output. By frequency dividing the output of the PLL and feeding it back and comparing it to a low frequency crystal-controlled reference clock, a stable high frequency clock may be generated. The VCO in a PLL typically has a range over which the frequency of the VCO may be voltage-controlled. In systems employing frequency scaling, it is desirable to have a voltage-controlled frequency range for normal voltage operation and another voltage-controlled frequency range for low voltage operation without resorting to two VCOs.
There is, therefore, a need for a way to have a VCO with two voltage-controlled frequency ranges which are logic selectable.
A voltage-controlled oscillator (VCO) has an odd number of logic inverters in a ring oscillator configuration. A transfer gate is connected across every two series inverters in a feed-forward configuration. The conductance of the transfer gate is varied with control voltages. The control voltages are adjusted within a feedback loop to control the frequency of the VCO. If the transfer gate circuits are OFF, the VCO operates at its lowest frequency and as the transfer gate circuits are turned ON by the control voltage, the frequency of the VCO increases until an upper frequency is achieved. A controlled inverter is coupled in parallel with each of the logic inverters using two metal oxide semiconductor (MOS) switch transistors. The two MOS switch transistors connect the inverters in one mode and disconnect the inverters in the second mode. The gates of the two MOS switches are controlled by a mode signal and the complement of the mode signal. When the controlled inverters are connected, the frequency range of the VCO is increased and when the inverters are disconnected the frequency range of the VCO reverts to its normal operating range. Within each frequency range of the VCO, the control voltages vary the frequency of the VCO.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.